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Broadband Modem Mixed-Signal Front End AD9868
FEATURES
Low cost 3.3 V CMOS MxFE for broadband modems 10-bit DAC converter 2x/4x interpolation filter 200 MSPS DAC update rate Integrated 17 dBm line driver with 19.5 dB gain control 10-bit, 80 MSPS, ADC converter -12 dB to +48 dB low noise RxPGA (<3 nV/Hz) Third-order, programmable low-pass filter Flexible digital data path interface Half- and full-duplex operation Pin compatible with the AD9865 Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in a 64-lead LFCSP_VQ
FUNCTIONAL BLOCK DIAGRAM
IOUTP+ IOUTP-
AD9868
PWRDWN MODE TXEN/TXSYNC TXCLK/TXQUIET ADIO[9:4]/ Tx[5:0] 10 2-4X TxDAC
0 TO -7.5dB
IAMP
0 TO -12dB
IOUTN+ IOUTN-
CLK SYNC. 2M CLK MULTIPLIER
CLKOUT1 CLKOUT2 OSCIN XTAL
ADIO[3:0]/ Rx[5:0]
10 RXEN/RXSYNC RXCLK AGC[5:0] PORT SPI PORT 6
06733-001
ADC 80MSPS
0 TO 6dB
2-POLE LPF
RX+
1-POLE LPF
APPLICATIONS
Broadband wireline networking
RX-
4
REGISTER = 1dB CONTROL
-6 TO +18dB -6 TO +24dB = 6dB = 6dB
Figure 1.
GENERAL DESCRIPTION
The AD9868 is a mixed-signal front-end (MxFE(R)) IC for transceiver applications requiring Tx path and Rx path functionality with data rates up to 80 MSPS. A lower cost, pincompatible version of the AD9865, the AD9868 removes the current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz. The part is well-suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9868 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks, from a single crystal or clock source. The Tx signal path consists of a 2x/4x low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier (IAMP) capable of delivering 17 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps. The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of -12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/Hz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or it can be simply bypassed. The 10-bit ADC achieves excellent dynamic performance up to an 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization. The AD9868 provides a highly integrated solution for many broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (-40C to +85C).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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AD9868 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Tx Path Specifications.................................................................. 3 Rx Path Specifications.................................................................. 4 Power Supply Specifications........................................................ 6 Digital Specifications ................................................................... 7 Serial Port Timing Specifications ............................................... 7 Half-Duplex Data Interface (ADIO Port) Timing Specifications ................................................................................ 8 Full-Duplex Data Interface (Tx and Rx Port) Timing Specifications ................................................................................ 8 Absolute Maximum Ratings............................................................ 9 Thermal Characteristics .............................................................. 9 Explanation of Test Levels ........................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Serial Port ........................................................................................ 12 Register Map Description.......................................................... 14 Serial Port Interface (SPI).......................................................... 14 Digital Interface .............................................................................. 16 Half-Duplex Mode ..................................................................... 16 Full-Duplex Mode ...................................................................... 17 RxPGA Control .......................................................................... 19 TxPGA Control .......................................................................... 20 Transmit Path.................................................................................. 21 Digital Interpolation Filters ...................................................... 21 TxDAC and IAMP Architecture .............................................. 22 Tx Programmable Gain Control .............................................. 23 TxDAC Output Operation........................................................ 23 IAMP Current-Mode Operation.............................................. 23 Receive Path .................................................................................... 24 Rx Programmable Gain Amplifier........................................... 24 Low-Pass Filter............................................................................ 25 Analog-to-Digital Converter (ADC)....................................... 26 AGC Timing Considerations.................................................... 27 Clock Synthesizer ........................................................................... 28 Power Control and Dissipation .................................................... 30 Power-Down ............................................................................... 30 Half-Duplex Power Savings ...................................................... 30 Power Reduction Options ......................................................... 31 Power Dissipation....................................................................... 33 Mode Select upon Power-Up and Reset.................................. 33 Analog and Digital Loopback Test Modes.............................. 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35
REVISION HISTORY
5/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD9868 SPECIFICATIONS
Tx PATH SPECIFICATIONS
AVDD = 3.3 V 5%, DVDD = CLKVDD = DRVDD = 3.3 V 10%, fOSCIN = 50 MHz, fDAC = 200 MHz, RSET = 2.0 k, unless otherwise noted. Table 1.
Parameter TxDAC DC CHARACTERISTICS Resolution Update Rate Full-Scale Output Current (IOUTP_FS) Gain Error 2 Offset Error Voltage Compliance Range TxDAC GAIN CONTROL CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy Gain Range Error TxDAC AC CHARACTERISTICS 3 Fundamental Signal-to-Noise and Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) IAMP DC CHARACTERISTICS IOUTN Full-Scale Current = IOUTN+ + IOUTN- AC Voltage Compliance Range IAMPN AC CHARACTERISTICS 4 Fundamental IOUTN SFDR (Third Harmonic) REFERENCE Internal Reference Voltage 5 Reference Error Reference Drift Tx DIGITAL FILTER CHARACTERISTICS (2x Interpolation) Latency (Relative to 1/fDAC) -0.2 dB Bandwidth -3 dB Bandwidth Stop-Band Rejection (0.289 fDAC to 0.711 fDAC) Tx DIGITAL FILTER CHARACTERISTICS (4x Interpolation) Latency (Relative to 1/fDAC) -0.2 dB Bandwidth -3 dB Bandwidth Stop Band Rejection (0.289 fOSCIN to 0.711 fOSCIN) PLL CLK MULTIPLIER OSCIN Frequency Range PLL M Factor Set to 2 PLL M Factor Set to 4 PLL M Factor Set to 8 Internal VCO Frequency Range Duty Cycle Temp Full Full Full 25C 25C Full 25C 25C 25C 25C 25C Test Level 1 Min Typ 10 II IV I V 2 2 2 -1 V V V IV V -7.5 0 0.5 Monotonic 2 0.5 63.1 63.2 -77.7 79.3 +1.5 200 25 Max Unit Bits MSPS mA % FS A V dB dB dB dB dB dBm dBc dBc dBc dBc mA V dBm dBc V % ppm/oC Cycles fOUT/fDAC fOUT/fDAC dB Cycles fOUT/fDAC fOUT/fDAC dB
Full Full Full Full Full Full 25C Full 25C Full Full Full Full Full Full Full Full Full Full
IV IV IV IV IV IV
62.0 62.5 67.1 2 1
-67.0
105 3.9 13 45.2 1.23 0.7 30 43 0.2187 0.2405 50 96 0.1095 0.1202 50
IV I V V V V V V V V V V
43.3
3.4
Full Full Full Full Full
Rev. 0 | Page 3 of 36
IV IV IV IV II
40 20 10 80 40
80 50 25 200 60
MHz MHz MHz MHz %
AD9868
Parameter OSCIN Impedance CLKOUT1 Jitter 6 CLKOUT2 Jitter 7 CLKOUT1 and CLKOUT2 Duty Cycle 8
1 2 3
Temp 25C 25C 25C Full
Test Level 1 V III III III
Min
Typ 10||03 12 6
Max
45
55
Unit ||pF ps rms ps rms %
See the Explanation of Test Levels section. Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input). TxDAC IOUTP_FS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 , fOUT = 5 MHz, 4x interpolation. 4 IOUTN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation. 5 Use external amplifier to drive additional load. 6 Internal VCO operates at 200 MHz; set to divide-by-1. 7 Because CLKOUT2 is a divided-down version of OSCIN, its jitter is typically equal to OSCIN. 8 CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.
Rx PATH SPECIFICATIONS
AVDD = 3.3 V 5%, DVDD = CLKVDD = DRVDD = 3.3 V 10%, half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted. Table 2.
Parameter Rx INPUT CHARACTERISTICS Input Voltage Span RxPGA Gain = -10 dB RxPGA Gain = +48 dB Input Common-Mode Voltage Differential Input Impedance Input Bandwidth with RxLPF Disabled, RxPGA = 0 dB Input Voltage Noise Density RxPGA Gain = 36 dB, f-3 dBF = 26 MHz RxPGA Gain = 48 dB, f-3 dBF = 26 MHz RxPGA CHARACTERISTICS Minimum Gain Maximum Gain Gain Step Size Gain Step Accuracy Gain Range Error RxLPF CHARACTERISTICS Cutoff Frequency (f-3 dBF ) Range Attenuation at 55.2 MHz with f-3 dBF = 21 MHz Pass-Band Ripple Settling Time 5 dB RxPGA Gain Step @ fADC = 50 MSPS 60 dB RxPGA Gain Step @ fADC = 50 MSPS ADC DC CHARACTERISTICS Resolution Conversion Rate Rx PATH LATENCY 2 Full-Duplex Interface Half-Duplex Interface Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 50 MSPS 3 RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Temp Test Level 1 Min Typ Max Unit
Full Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full 25C 25C 25C 25C N/A Full Full Full
III III III III III III III III III III III III III III III III III N/A II V V 15
6.33 8 1.3 400||4.0 53 3.0 2.4 -12 48 1 Monotonic 0.5 35 20 1 20 100 10 20 10.5 10.0 80
V p-p mV p-p
V
||pF MHz nV/Hz nV/Hz dB dB dB dB dB MHz dB dB ns ns Bits MSPS Cycles Cycles
25C 25C
III III
43.7 -71
dBc dBc
Rev. 0 | Page 4 of 36
AD9868
Parameter RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise and Distortion (SINAD) Total Harmonic Distortion (THD) Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 80 MSPS 4 RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output) RxPGA Gain = 40 dB IOUTP Pins to RX Pins RxPGA Gain = 0 dB IOUTP Pins to RX Pins
1 2 3
Temp 25C 25C Full Full
Test Level 1 III III IV IV
Min
Typ 59 -67.2
Max
Unit dBc dBc dBc dBc
58
59 -66
-62.9
25C 25C 25C 25C 25C 25C
III III III III II II 58.9
41.8 -67 58.6 -62.9 59.6 -69.7
dBc dBc dBc dBc dBc dBc
-59.8
25C 25C
III III
83 123
dBc dBc
See the Explanation of Test Levels section. Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC. fIN = 5 MHz, AIN = -1.0 dBFS, LPF cutoff frequency set to 15.5 MHz with Register 0x08 = 0x80. 4 fIN = 5 MHz, AIN = -1.0 dBFS, LPF cutoff frequency set to 26 MHz with Register 0x08 = 0x80.
Rev. 0 | Page 5 of 36
AD9868
POWER SUPPLY SPECIFICATIONS
AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V, RSET = 2 k, full-duplex operation with fDATA = 80 MSPS 1 , unless otherwise noted. Table 3.
Parameter SUPPLY VOLTAGES AVDD CLKVDD DVDD DRVDD IS_TOTAL (Total Supply Current) POWER CONSUMPTION IAVDD + ICLKVDD (Analog Supply Current) IDVDD + IDRVDD (Digital Supply Current) POWER CONSUMPTION (Half-Duplex Operation with fDATA = 50 MSPS) 3 Tx Mode IAVDD + ICLKVDD IDVDD + IDRVDD Rx Mode IAVDD + ICLKVDD IDVDD + IDRVDD POWER CONSUMPTION OF FUNCTIONAL BLOCKS1 (IAVDD + ICLKVDD) RxPGA and LPF ADC TxDAC IAMP (Programmable) Reference CLK PLL and Synthesizer MAXIMUM ALLOWABLE POWER DISSIPATION STANDBY POWER CONSUMPTION IS_TOTAL (Total Supply Current) POWER-DOWN DELAY (Using PWRDWN Pin) RxPGA and LPF ADC TxDAC IAMP CLK PLL and Synthesizer POWER-UP DELAY (Using PWRDWN Pin) RxPGA and LPF ADC TxDAC IAMP CLK PLL and Synthesizer
1 2
Temp Full Full Full Full Full Full Full
Test Level 2 V V V V II IV IV
Min 3.135 3.0 3.0 3.0
Typ 3.3 3.3 3.3 3.3 406 311 95
Max 3.465 3.6 3.6 3.6 475 342 133
Unit V V V V mA mA mA
25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
IV IV IV IV III III III III III III IV
112 46 225 36.5 87 108 38 10 170 107
130 49.5 253 39
mA mA mA mA mA mA mA mA mA mA W mA ns ns ns ns ns s ns s ns s
100
1.66 13
III III III III III III III III III III
440 12 20 20 27 7.8 88 13 20 20
Default power-up settings for MODE = high and CONFIG = low, IOUTP_FS = 20 mA, does not include IAMP current consumption, which is application dependent. See the Explanation of Test Levels section. 3 Default power-up settings for MODE = low and CONFIG = low.
Rev. 0 | Page 6 of 36
AD9868
DIGITAL SPECIFICATIONS
AVDD = 3.3 V 5%, DVDD = CLKVDD = DRVDD = 3.3 V 10%, RSET = 2 k, unless otherwise noted. Table 4.
Parameter CMOS LOGIC INPUTS High Level Input Voltage Low Level Input Voltage Input Leakage Current Input Capacitance CMOS LOGIC OUTPUTS (CLOAD = 5 pF) High Level Output Voltage (IOH = 1 mA) Low Level Output Voltage (IOH = 1 mA) Output Rise/Fall Time High Strength Mode and CLOAD = 15 pF Low Strength Mode and CLOAD = 15 pF High Strength Mode and CLOAD = 5 pF Low Strength Mode and CLOAD = 5 pF RESET Minimum Low Pulse Width (Relative to fADC)
1
Temp Full Full Full Full Full Full Full Full Full
Test Level 1 VI VI VI VI VI VI VI VI VI
Min DRVDD - 0.7
Typ
Max
Unit V V A pF V V ns ns ns ns Clock cycles
0.4 12 3 DRVDD - 0.7 0.4 1.5/2.3 1.9/2.7 0.7/0.7 1.0/1.0 1
See the Explanation of Test Levels section.
SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V 5%, DVDD = CLKVDD = DRVDD = 3.3 V 10%, unless otherwise noted. Table 5.
Parameter WRITE OPERATION (See Figure 5) SCLK Clock Rate (fSCLK) SCLK Clock High (tHI) SCLK Clock Low (tLOW) SDIO to SCLK Setup Time (tDS) SCLK to SDIO Hold Time (tDH) SEN to SCLK Setup Time (tS) SCLK to SEN Hold Time (tH) READ OPERATION (See Figure 6 and Figure 7) SCLK Clock Rate (fSCLK) SCLK Clock High (tHI) SCLK Clock Low (tLOW) SDIO to SCLK Setup Time (tDS) SCLK to SDIO Hold Time (tDH) SCLK to SDIO (or SDO) Data Valid Time (tDV) SEN to SDIO Output Valid to High-Z (tEZ)
1
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Test Level 1 IV IV IV IV IV IV IV IV IV IV IV IV IV IV
Min
Typ
Max 32
Unit MHz ns ns ns ns ns ns MHz ns ns ns ns ns ns
14 14 14 0 14 0 32 14 14 14 0 14 2
See the Explanation of Test Levels section.
Rev. 0 | Page 7 of 36
AD9868
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V 5%, DVDD = CLKVDD = DRVDD = 3.3 V 10%, unless otherwise noted. Table 6.
Parameter READ OPERATION 2 (See Figure 9) Output Data Rate Three-State Output Enable Time (tPZL) Three-State Output Disable Time (tPLZ) Rx Data Valid Time (tVT) Rx Data Output Delay (tOD) WRITE OPERATION (See Figure 8) Input Data Rate (2x Interpolation) Input Data Rate (4x Interpolation) Tx Data Setup Time (tDS) Tx Data Hold Time (tDH) Latch Enable Time (tEN) Latch Disable Time (tDIS)
1 2
Temp Full Full Full Full Full Full Full Full Full Full Full
Test Level 1 II II II II II II II II II II II
Min 20
Typ
Max 80 3 3 4
Unit MSPS ns
ns
ns ns MSPS MSPS ns ns ns ns
1.5
40 20 1 2.5
80 50
3 3
See the Explanation of Test Levels section. CLOAD = 5 pF for digital data outputs.
FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V 5%, DVDD = CLKVDD = DRVDD = 3.3 V 10%, unless otherwise noted. Table 7.
Parameter Tx PATH INTERFACE (See Figure 12) Input Nibble Rate (2x Interpolation) Input Nibble Rate (4x Interpolation) Tx Data Setup Time (tDS) Tx Data Hold Time (tDH) Rx PATH INTERFACE 2 (See Figure 13) Output Nibble Rate Rx Data Valid Time (tDV) Rx Data Hold Time (tDH)
1 2
Temp Full Full Full Full Full Full Full
Test Level 1 II II II II II II II
Min 80 40 2.5 1.5 40 3 0
Typ
Max 160 100
Unit MSPS MSPS ns ns MSPS ns ns
160
See the Explanation of Test Levels section. CLOAD = 5 pF for digital data outputs.
Rev. 0 | Page 8 of 36
AD9868 ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter ELECTRICAL AVDD, CLKVDD Voltage DVDD, DRVDD Voltage RX+, RX-, REFT, REFB IOUTP+, IOUTP- IOUTN+, IOUTN- OSCIN, XTAL REFIO, REFADJ Digital Input and Output Voltage Digital Output Current ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating 3.9 V maximum 3.9 V maximum -0.3 V to AVDD + 0.3 V -1.5 V to AVDD + 0.3 V -0.3 V to +3.9 V -0.3 V to CLVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DRVDD + 0.3 V 5 mA maximum -40C to +85C
THERMAL CHARACTERISTICS
Thermal Resistance: 64-lead LFCSP (4-layer board). JA = 24C/W (paddle soldered to ground plane, 0 LPM air). JA = 30.8C/W (paddle not soldered to ground plane, 0 LPM air).
EXPLANATION OF TEST LEVELS
I. II. III. 100% production tested. 100% production tested at 25C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C and guaranteed by design and characterization for industrial temperature range.
125C 150C -65C to +150C
IV. V. VI.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 9 of 36
AD9868 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PWRDWN CLKOUT2 CLKVDD CLKVSS CONFIG IOUTN+
50
IOUTP+
IOUTP-
DRVDD
DRVSS
OSCIN
MODE
DVDD
DVSS
XTAL
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
49
ADIO9/Tx[5] ADIO8/Tx[4] ADIO7/Tx[3] ADIO6/Tx[2] ADIO5/Tx[1] ADIO4/Tx[0] ADIO3/Rx[5] ADIO2/Rx[4] ADIO1/Rx[3]
1 2 3 4 5 6 7 8 9
48 47
AVSS AVSS IOUTN- NC AVSS AVDD REFIO REFADJ AVDD AVSS RX+ RX- AVSS AVDD AVSS REFT
PIN 1 IDENTIFIER
46 45 44 43
AD9868
TOP VIEW (Not to Scale)
42 41 40 39 38 37 36 35 34 33
ADIO0/Rx[2] 10 NC/Rx[1]
11
NC/Rx[0] 12 RXEN/RXSYNC 13 TXEN/TXSYNC 14 TXCLK/TXQUIET 15 RXCLK 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DRVSS
SDIO
CLKOUT1
GAIN/PGA[5]
SCLK
AVSS
SEN
PGA[4]
PGA[3]
PGA[2]
PGA[1]
DRVDD
PGA[0]
RESET
REFB
SDO
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. 1 2 to 5 6 7 8, 9 10 11 12 13 14 15 16 Mnemonic ADIO9 Tx[5] ADIO8 to ADIO5 Tx[4:1] ADIO4 Tx[0] ADIO3 Rx[5] ADIO2, ADIO1 Rx[4:3] ADIO0 Rx[2] NC Rx[1] NC Rx[0] RXEN RXSYNC TXEN TXSYNC TXCLK TXQUIET RXCLK Mode 1 HD FD HD FD HD FD HD FD HD FD HD FD HD FD HD FD HD FD HD FD HD FD HD FD Description MSB of ADIO Buffer. MSB of Tx Nibble Input. Bit 8 to Bit 5 of ADIO Buffer. Bit 4 to Bit 1 of Tx Nibble Input. Bit 4 of ADIO Buffer. LSB of Tx Nibble Input. Bit 3 of ADIO Buffer. MSB of Rx Nibble Output. Bit 2 to Bit 1 of ADIO Buffer. Bit 4 to Bit 3 of Rx Nibble Output. LSB of ADIO Buffer. Bit 2 of Rx Nibble Output. No Connect. Bit 1 of Rx Nibble Output. No Connect. LSB of Rx Nibble Output. ADIO Buffer Control Input. Rx Data Synchronization Output. Tx Path Enable Input. Tx Data Synchronization Input. ADIO Sample Clock Input. Fast TxDAC/IAMP Power-Down. ADIO Request Clock Input. Rx and Tx Clock Output at 2 x fADC.
Rev. 0 | Page 10 of 36
06733-002
AD9868
Pin No. 17, 64 18, 63 19 20 21 22 23 24 25 to 29 30 31, 34, 36, 39, 44, 47, 48 32, 33 35, 40, 43 37, 38 41 42 45, 49 46 50 51 52 53 54 55 56 57 58 59 60 61 62
1
Mnemonic DRVDD DRVSS CLKOUT1 SDIO SDO SCLK SEN GAIN PGA[5] PGA[4:0] RESET AVSS REFB, REFT AVDD RX-, RX+ REFADJ REFIO NC IOUTN- IOUTN+ IOUTP- IOUTP+ MODE CONFIG CLKVSS XTAL OSCIN CLKVDD DVSS DVDD CLKOUT2 PWRDWN
Mode 1
FD HD or FD HD or FD
Description Digital Output Driver Supply Input. Digital Output Driver Supply Return. fADC/N Clock Output (R = 1, 2, or 3). Serial Port Data Input/Output. Serial Port Data Output. Serial Port Clock Input. Serial Port Enable Input. Tx Data Port (Tx[5:0]) Mode Select. MSB of PGA Input Data Port. Bit 4 to Bit 0 of PGA Input Data Port. Reset Input (Active Low). Analog Supply Return. ADC Reference Decoupling Nodes. Analog Power Supply Input. Receive Path - and + Analog Inputs. TxDAC Full-Scale Current Adjust. TxDAC Reference Input/Output. Do Not Connect; Leave Open. -Tx Mirror Current Output Sink. +Tx Mirror Current Output Sink. -TxDAC Current Output Source. +TxDAC Current Output Source. Digital Interface Mode Select Input, Low = HD, High = FD. Power-Up SPI Register Default Setting Input. Clock Oscillator/Synthesizer Supply Return. Crystal Oscillator Inverter Output. Crystal Oscillator Inverter Input. Clock Oscillator/Synthesizer Supply. Digital Supply Return. Digital Supply Input. fOSCIN/L Clock Output (L = 1, 2, or 4). Power-Down Input.
HD = half-duplex mode; FD = full-duplex mode.
Rev. 0 | Page 11 of 36
AD9868 SERIAL PORT
Table 10. SPI Register Mapping
Power-Up Default Value MODE = 0 MODE = 1 (Half-Duplex) (Full-Duplex) CONFIG = 0 CONFIG = 1 CONFIG = 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0xFF 0xFF 0xFF 0xFF 0 00 01 0 0 0 01 0 0 01 0 0 0 0 1 0x80 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0xFF 0xFF 0xFF 0xFF 0 00 10 0 0 0 01 0 0 01 0 0 0 1 1 0x61 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 N/A N/A N/A N/A 0 00 01 0 0 0 01 0 0 01 0 0 0 0 1 0x80
Address Bit 1 Description Width (Hex) SPI PORT CONFIGURATION AND SOFTWARE RESET 0x00 7 4-Wire SPI 1 6 SPI LSB First 1 5 Software Reset 1 POWER CONTROL REGISTERS (Via PWRDWN Pin) 0x01 7 CLK Synthesizer 1 6 TxDAC/IAMP 1 5 Tx Digital 1 4 REF 1 3 ADC CML 1 2 ADC 1 1 PGA Bias 1 0 RxPGA 1 0x02 7 CLK Synthesizer 1 6 TxDAC/IAMP 1 5 Tx Digital 1 4 REF 1 3 ADC CML 1 2 ADC 1 1 PGA Bias 1 0 RxPGA 1 HALF-DUPLEX POWER CONTROL 0x03 7:3 Tx OFF Delay 5 2 Rx_TXEN 1 1 Tx PWRDN 1 0 Rx PWRDN 1 PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL 0x04 4 fADC from PLL 1 3:2 PLL Divide-N 2 1:0 PLL Multiplier-M 2 0x05 2 OSCIN to RXCLK 1 1 Invert RXCLK 1 0 Disable RXCLK 1 0x06 7:6 CLKOUT2 Divide 2 5 CLKOUT2 Invert 1 4 CLKOUT2 Disable 1 3:2 CLKOUT1 Divide 2 1 CLKOUT1 Invert 1 0 CLKOUT1 Disable 1 Rx PATH CONTROL 0x07 5 Initiate Offset Cal. 1 4 Rx Low Power 1 0 Enable Rx LPF 1 0x08 7:0 8 Rx Filter Target Cutoff Frequency
Comments Default SPI configuration is 3-wire, MSB first.
PWRDWN = 0. Default setting is for all blocks powered on.
PWRDWN = 1. Default setting is for all functional blocks powered down except PLL.
Default setting is for TXEN input to control power-on/power-off of Tx/Rx path. Tx driver delayed by 31 1/fDATA clock cycles.
Full-duplex RXCLK normally at nibble rate.
Default setting is CLKOUT2 and CLKOUT1 enabled with divide-by-2.
Default setting has LPF on. Rx path at nominal power bias setting for CONFIG = 0 and low power for CONFIG = 1. Refer to the Low-Pass Filter section.
Rev. 0 | Page 12 of 36
AD9868
Power-Up Default Value MODE = 0 MODE = 1 (Half-Duplex) (Full-Duplex) CONFIG = 0 CONFIG = 1 CONFIG = 0 0x00 0x00 0x7F 0x7F 0 1 0 0 1 00 0 N/A N/A 0 0 0 0 N/A 0 N/A N/A 0 0 0 0 0x00 0x04 0x04 0x01 0x01 0x00 0x00 0x00 0x7F 0x7F 0 1 0 1 0 01 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0x00 0x04 0x04 0x01 0x01 0x00 N = 0, 1, 2, 3, 4. Standing current. Default setting is for high drive strength and IAMP enabled. Data format is straight binary for half-duplex and twos complement for full-duplex interface. Analog loopback: ADC Rx data fed back to TxDAC. Digital loopback: Tx input data to Rx output port.
Address Bit 1 Description Width (Hex) Tx/Rx PATH GAIN CONTROL 0x09 6 Enable SPI Rx Gain 1 0x00 5:0 Rx Gain Code 6 0x00 0x0A 6 Enable SPI Tx Gain 1 0x7F 5:0 Tx Gain Code 6 0x7F TxPGA AND RxPGA CONTROL 0x0B 6 PGA Code for Tx 1 0 5 PGA Code for Rx 1 1 3 Force Gain Strobe 1 0 2 Rx Gain on Tx Port 1 0 1 3-Bit RxPGA Port 1 0 Tx DIGITAL FILTER AND INTERFACE 0x0C 7:6 2 01 Interpolation Factor 4 1 0 Invert TXEN/TXSYNC 3 Tx 5/5 Nibble 2 1 N/A 2 LS Nibble First2 1 N/A 1 TXCLK Neg. Edge 1 0 0 Twos Complement 1 0 Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK 0x0D 7 Analog Loopback 1 0 6 Digital Loopback2 1 0 5 Rx Port Three-State 1 N/A 4 1 0 Invert RXEN/RXSYNC 3 Rx 5/5 Nibble 1 N/A 2 LS Nibble First 1 N/A 1 RXCLK Neg. Edge 1 0 0 Twos Complement 1 0 DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID 0x0E 7 1 0 Low Digital Drive Strength 0 TxDAC Output 1 0 0x0F 3:0 REV ID Number 4 0x00 Tx IAMP GAIN AND BIAS CONTROL 0x10 7 Select Tx Gain 1 0x04 2:0 N 3 0x04 0x12 6:4 Standing Current 3 0x01 2:0 3 0x01 IOFF1 Standing Current 0x13 7:5 CPGA Bias Adjust 3 0x00 4:3 SPGA Bias Adjust 2 2:0 ADC Bias Adjust 4
1 2
Comments Default setting is for hardware Rx gain code via PGA or Tx data port. Default setting is for Tx gain code via SPI control. Default setting is RxPGA control active via PGA port.
Default setting is 2x interpolation with LPF response. Data format is straight binary for half-duplex and twos complement for full-duplex interface.
Current bias setting for Rx path's functional blocks. Refer to the Power Reduction Options section.
Bits that are undefined should always be assigned a 0. Full-duplex only.
Rev. 0 | Page 13 of 36
AD9868
REGISTER MAP DESCRIPTION
The AD9868 contains a set of programmable registers (see Table 10) that are used to optimize its numerous features, interface options, and performance parameters from its default register settings. Registers pertaining to similar functions have been grouped together and assigned adjacent addresses to minimize the update time when using the multibyte serial port interface (SPI) read/write feature. Bits that are undefined within a register should be assigned a 0 when writing to that register. The default register settings are intended to allow some applications to operate without using an SPI. The AD9868 can be configured to support a half- or full-duplex digital interface via the MODE pin, with each interface having two possible default register settings determined by the setting of the CONFIG pin. For instance, applications that need to use only the Tx or Rx path functionality can configure the AD9868 for a half-duplex interface (MODE = 0), and use the TXEN pin to select between the Tx or Rx signal path with the unused path remaining in a reduced power state. The CONFIG pin can be used to select the default interpolation ratio of the Tx path and RxPGA gain mapping. An 8-bit instruction header must accompany each read and write operation. The instruction header is shown in Table 12. The MSB is an R/W indicator bit with logic high indicating a read operation. The next two bits, N1 and N0, specify the number of bytes (one to four bytes) to be transferred during the data transfer cycle. The remaining five bits specify the address bits to be accessed during the data transfer portion. The data bits immediately follow the instruction header for both read and write operations. Table 12. Instruction Header Information
MSB 17 R/W 16 N1 15 N0 14 A4 13 A3 12 A2 11 A1 LSB 10 A0
SERIAL PORT INTERFACE (SPI)
The serial port of the AD9868 has 3-wire or 4-wire SPI capability allowing read/write access to all registers that configure the device's internal parameters. Registers pertaining to the SPI are listed in Table 11. The default 3-wire serial communication port consists of a clock (SCLK), serial port enable (SEN), and a bidirectional data (SDIO) signal. SEN is an active low, control gating, read and write cycle. When SEN is high, SDO and SDIO are threestated. The inputs to SCLK, SEN, and SDIO contain a Schmitt trigger with a nominal hysteresis of 0.4 V centered about DRVDD/2. The SDO pin remains three-stated in a 3-wire SPI interface. Table 11. SPI Registers Pertaining to SPI Options
Address (Hex) 0x00 Bit 7 6 Description Enable 4-wire SPI. Enable SPI LSB first.
The AD9868 serial port can support both MSB (most significant bit) first and LSB (least significant bit) first data formats. Figure 3 illustrates how the serial port words are built for the MSB first and Figure 4 illustrates LSB first modes. The bit order is controlled by the SPI LSB first bit (Register 0x00, Bit 6). The default value is 0, MSB first. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. The AD9868 automatically decrements the address for each successive byte required for the multibyte communication cycle.
SEN SCLK SDATA
R/W N1 N2 A4 A3 A2 A1 A0 D71 D61 D1N D0N
06733-003
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
Figure 3. SPI Timing, MSB First
SEN SCLK SDATA
A0 A1 A2 A3 A4 N2 N1 R/W D01 D11 D6N D7N
06733-004
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
Figure 4. SPI Timing, LSB First
A 4-wire SPI can be enabled by setting the 4-wire SPI bit high, causing the output data to appear on the SDO pin instead of on the SDIO pin. The SDIO pin serves as an input-only throughout the read operation. Note that the SDO pin is active only during the transmission of data and remains three-stated at any other time.
When the SPI LSB first bit is set high, the serial port interprets both instruction and data bytes LSB first. Multibyte data transfers in LSB format can be completed by writing an instruction byte that includes the register address of the first address to be accessed. The AD9868 automatically increments the address for each successive byte required for the multibyte communication cycle.
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AD9868
Figure 5 illustrates the timing requirements for a write operation to the SPI port. After the serial port enable (SEN) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To initiate a write operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles. If a multibyte communication cycle is specified, the destination address is decremented (MSB first) and shifts in another eight bits of data. This process repeats until all the bytes specified in the instruction header (N1 bit, N0 bit) are shifted into the SDIO pin. SEN must remain low during the data transfer operation, only going high after the last bit is shifted into the SDIO pin. Figure 6 illustrates the timing for a 3-wire read operation to the SPI port. After SEN goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles. If a multibyte communication cycle is specified in the instruction header, a similar process as previously described for a multibyte SPI write operation applies. The SDO pin remains three-stated in a 3-wire read operation. Figure 7 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception of the data appearing at the SDO pin, while the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times.
SEN
tS 1/fSCLK tHI tLOW
tH
SCLK
tDS
SDIO
R/W
N1
N0
A0
D7
D6 D1
D0
Figure 5. SPI Write Operation Timing
SEN
tS 1/fSCLK tHI tLOW tDV
N1 A2 A1 A0 D7 D6 D1 D0
SCLK
06733-006
06733-007
tDS
SDIO
tDH
R/W
tEZ
Figure 6. SPI 3-Wire Read Operation Timing
SEN
tS 1/fSCLK tHI tLOW
SCLK
tDS
SDIO
tDH
R/W N1 A2 A1 A0
tEZ tDV tEZ
D7 D6 D1 D0
SDO
Figure 7. SPI 4-Wire Read Operation Timing
Rev. 0 | Page 15 of 36
06733-005
tDH
AD9868 DIGITAL INTERFACE
The digital interface port is configurable for half-duplex or fullduplex operation by pin strapping the MODE pin low or high, respectively. In half-duplex mode, the digital interface port becomes a 10-bit bidirectional bus called the ADIO port. In full-duplex mode, the digital interface port is divided into two 6-bit ports called Tx[5:0] and Rx[5:0] for simultaneous Tx and Rx operations. In this mode, data is transferred between the ASIC and AD9868 in 6-bit (or 5-bit) nibbles. The AD9868 also features a flexible digital interface for updating the RxPGA and TxPGA gain registers via a 6-bit PGA port or Tx[5:0] port for fast updates, or via the SPI port for slower updates. See the RxPGA Control section for more information. The output from the receive path is driven onto the ADIO bus when the RXEN pin is high and when a clock is present on the RXCLK pin. While the output latch is enabled by RXEN, valid data appears on the bus after a 6-clock-cycle delay due to the internal FIFO delay. Note that Rx data is not latched back into the Tx path if TXEN is high during this interval with TXCLK present. The ADIO bus becomes three-stated once the RXEN pin returns low. Figure 9 shows the receive path output timing.
RXCLK RXEN ADIO[9:0]
tPZL tVT
RX0 RX1
tOD tPLZ
RX2 RX3
06733-009
HALF-DUPLEX MODE
The half-duplex mode is selected when the MODE pin is tied low. In this mode, the bidirectional ADIO port is typically shared in burst fashion between the transmit path and receive path. Two control signals, TXEN and RXEN, from a DSP (or digital ASIC) control the bus direction by enabling the ADIO port's input latch and output driver, respectively. Two clock signals are also used, TXCLK to latch the Tx input data, and RXCLK to clock the Rx output data. The ADIO port can be disabled by setting TXEN and RXEN low (default setting), thus allowing it to be connected to a shared bus. Internally, the ADIO port consists of an input latch for the Tx path in parallel with an output latch with three-state outputs for the Rx path. TXEN is used to enable the input latch; RXEN is used to three-state the output latch. A five-sample-deep FIFO is used on the Tx and Rx paths to absorb any phase difference between the AD9868 internal clocks and the externally supplied clocks (TXCLK, RXCLK). The ADIO bus accepts input datawords into the transmit path when the TXEN pin is high, the RXEN pin is low, and a clock is present on the TXCLK pin, as shown in Figure 8.
tDS
TXCLK TXEN ADIO[9:0]
Figure 9. Receive Data Output Timing Diagram
To add flexibility to the digital interface port, several programming options are available in the SPI registers. These options are listed in Table 13. The default Tx and Rx data input formats are straight binary, but can be changed to twos complement. The default TXEN and RXEN settings are active high, but can be set to opposite polarities, thus allowing them to share the same control. In this case, the ADIO port can still be placed onto a shared bus by disabling its input latch via the control signal, and disabling the output driver via the SPI register. The clock timing can be independently changed on the transmit and receive paths by selecting either the rising or falling clock edge as the validating/sampling edge of the clock. Lastly, the output driver strength can be reduced for lower data rate applications. Table 13. SPI Registers for Half-Duplex Interface
Address (Hex) 0x0C Bit 4 1 0 5 4 1 0 7 Description Invert TXEN. TXCLK negative edge. Twos complement. Rx port three-state. Invert RXEN. RXCLK negative edge. Twos complement. Low digital drive strength.
0x0D
tEN
TX0 TX1
tDH
TX2 TX3
tDIS
TX4
06733-008
0x0E
RXEN
Figure 8. Transmit Data Input Timing Diagram
The Tx interpolation filter(s) following the ADIO port can be flushed with zeros if the clock signal into the TXCLK pin is present for 33 clock cycles after TXEN goes low. Note that the data on the ADIO bus is irrelevant over this interval.
The half-duplex interface can be configured to act as a slave or a master to the digital ASIC. An example of a slave configuration is shown in Figure 10. In this example, the AD9868 accepts all the clock and control signals from the digital ASIC. Because the sampling clocks for the DAC and ADC are derived internally from the OSCIN signal, the TXCLK and RXCLK signals must be at exactly the same frequency as the OSCIN signal. The phase relationships among the TXCLK, RXCLK, and OSCIN signals can be arbitrary. If the digital ASIC cannot provide a low jitter clock source to OSCIN, use the AD9868 to generate the clock for its DAC and ADC and to pass the desired clock signal to the digital ASIC via CLKOUT1 or CLKOUT2.
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AD9868
DIGITAL ASIC
ADIO [9:0] Tx/Rx DATA[9:0]
AD9868
10 TO Tx DIGITAL FILTER FROM Rx ADC
10
In either application, Tx data and Rx data are transferred between the ASIC and AD9868 in 6-bit (or 5-bit) nibbles at twice the internal input/output word rates of the Tx interpolation filter and ADC. Note that the TxDAC update rate must not be less than the nibble rate. Therefore, the 2x or 4x interpolation filter must be used with a full-duplex interface. The AD9868 acts as the master, providing RXCLK as an output clock that is used for the timing of both the Tx[5:0] and Rx[5:0] ports. RXCLK always runs at the nibble rate and can be inverted or disabled via an SPI register. Because RXCLK is derived from the clock synthesizer, it remains active provided that this functional block remains powered on. A buffered version of the signal appearing at OSCIN can also be directed to RXCLK by setting Bit 2 of Register 0x05. This feature allows the AD9868 to be completely powered down (including the clock synthesizer) while serving as the master. The Tx[5:0] port operates in the following manner with the SPI register default settings: 1. Two consecutive nibbles of the Tx data are multiplexed together to form a 10-bit data-word in twos complement format. The clock appearing on the RXCLK pin is a buffered version of the internal clock used by the Tx[5:0] port's input latch with a frequency that is always twice the ADC sample rate (2 x fADC). Data from the Tx[5:0] port is read on the rising edge of this sampling clock, as illustrated in the timing diagram shown in Figure 12. Note that TXQUIET must remain high for the reconstructed Tx data to appear as an analog signal at the output of the TxDAC or IAMP. The TXSYNC signal is used to indicate which word belongs to which nibble. While TXSYNC is low, the first nibble of every word is read as the most significant nibble. The second nibble of that same word is read on the following TXSYNC high level as the least significant nibble. If TXSYNC is low for more than one clock cycle, the last transmit data is read continuously until TXSYNC is brought high for the second nibble of a new transmit word. This feature can be used to flush the interpolator filters with zeros. Note that the GAIN signal must be kept low during a Tx operation.
tDS tSU
RXCLK
RXEN TXEN DACCLK ADCCLK CLKOUT
RXEN TXEN TXCLK RXCLK
06733-010
OSCIN
Figure 10. Example of a Half-Duplex Digital Interface with AD9868 Serving as the Slave
Figure 11 shows a half-duplex interface with the AD9868 acting as the master, generating all the required clocks. CLKOUT1 provides a clock equal to the bus data rate that is fed to the ASIC as well as back to the TXCLK and RXCLK inputs. This interface has the advantage of reducing the digital ASIC pin count by three. The ASIC needs only to generate a bus control signal that controls the data flow on the bidirectional bus.
DIGITAL ASIC
ADIO [9:0] Tx/Rx DATA[9:0]
AD9868
10 TO Tx DIGITAL FILTER FROM Rx ADC
2.
10
3.
RXEN BUS_CTR TXEN TXCLK RXCLK CLKIN CLKOUT1 OSCIN FROM CRYSTAL OR MASTER CLK
06733-011
4.
Figure 11. Example of a Half-Duplex Digital Interface with AD9868 Serving as the Master
FULL-DUPLEX MODE
The full-duplex mode interface is selected when the MODE pin is tied high. It can be used for full- or half-duplex applications. The digital interface port is divided into two 6-bit ports called Tx[5:0] and Rx[5:0], allowing simultaneous Tx and Rx operations for full-duplex applications. In half-duplex applications, the Tx[5:0] port can also be used to provide a fast update of the RxPGA during an Rx operation. This feature is enabled by default and can be used to reduce the required pin count of the ASIC (refer to RxPGA Control section for details).
TXSYNC
t tDHHD
06733-012
Tx[5:0]
Tx0LSB
Tx1MSB
Tx1LSB
Tx2MSB
Tx3LSB Tx 2 LSB
Tx3MSB
Figure 12. Tx[5:0] Port Full-Duplex Timing Diagram
Rev. 0 | Page 17 of 36
AD9868
The Rx[5:0] port operates in the following manner with the SPI register default settings: 1. Two consecutive nibbles of the Rx data are multiplexed together to form a 10-bit data-word in twos complement format. The Rx data is valid on the rising edge of RXCLK, as illustrated in the timing diagram shown in Figure 13. The RXSYNC signal is used to indicate which word belongs to which nibble. While RXSYNC is low, the first nibble of every word is transmitted as the most significant nibble. The second nibble of that same word is transmitted on the following RXSYNC high level as the least significant nibble.
tDH
RXCLK
2. 3.
The default Tx and Rx data input formats are twos complement, but can be changed to straight binary. The default TXSYNC and RXSYNC settings can be changed such that the first nibble of the word appears while either TXSYNC, RXSYNC, or both are high. In addition, the least significant nibble can be selected as the first nibble of the word (least significant nibble first). The output driver strength can also be reduced for lower data rate applications. For the AD9868, the most significant nibble defaults to 6 bits, and the least significant nibble defaults to 4 bits. This can be changed so that the least significant nibble and most significant nibble have 5 bits each. To accomplish this, set the 5/5 nibble bit (Bit 3 in Register 0x0C and Bit 3 in Register 0x0D), and use the Tx[5:1] and Rx[5:1] data pins. Figure 14 shows a possible digital interface between an ASIC and the AD9868. The AD9868 serves as the master generating the required clocks for the ASIC. This interface requires that the ASIC reserve 16 pins for the interface, assuming a 6-bit nibble width and the use of the Tx port for RxPGA gain control. Note that the ASIC pin allocation can be reduced by 3 if a 5-bit nibble width is used and the gain (or gain strobe) of the RxPGA is controlled via the SPI port.
DIGITAL ASIC
OPTIONAL GAIN
RXSYNC
tDV
06733-013
Rx[5:0]
Rx0LSB
Rx1MSB
Rx1LSB
Rx2MSB
Rx3LSB
Rx3MSB
Figure 13. Full-Duplex Rx Port Timing
Tx DATA[5:0]
Table 14. SPI Registers for Full-Duplex Interface
Address (Hex) 0x05 Bit 2 1 0 2 4 3 2 1 0 5 4 3 2 1 0 7 Description OSCIN to RXCLK. Invert RXCLK. Disable RXCLK. Rx gain on Tx port. Invert TXSYNC. Tx 5/5 nibble. LS nibble first. TXCLK negative edge. Twos complement. Rx port three-state. Invert RXSYNC. Rx 5/5 nibble. LS nibble first. RXCLK negative edge. Twos complement. Low digital drive strength.
Rx DATA[5:0]
Rx[5:0]
MUX
DEMUX
To add flexibility to the full-duplex digital interface port, several programming options are available in the SPI registers. These options are listed in Table 14. The timing for the Tx[5:0] and/or Rx[5:0] ports can be independently changed by selecting either the rising or falling clock edge as the sampling/validating edge of the clock. Inverting RXCLK (via Bit 1 of Register 0x05) affects both the Rx and Tx interface because they both use RXCLK.
AD9868/AD9869
6 TO RxPGA
Tx[5:0]
10/12
TO Tx DIGITAL FILTER
10/12
FROM RxADC
RX_SYNC TX_SYNC CLKIN
RXSYNC TXSYNC RXCLK CLKOUT1 CLKOUT2
0x0B 0x0C
OSCIN FROM CRYSTAL OR MASTER CLK
06733-014
0x0D
Figure 14. Example of a Full-Duplex Digital Interface with Optional RxPGA Gain Control via Tx[5:0]
0x0E
Rev. 0 | Page 18 of 36
AD9868
RxPGA CONTROL
The AD9868 contains a digital PGA in the Rx path that is used to extend the dynamic range. The RxPGA can be programmed over -12 dB to +48 dB with 1 dB resolution using a 6-bit word, and with a 0 dB setting corresponding to a 2 V p-p input signal. The 6-bit word is fed into a look-up table (LUT) that is used to distribute the desired gain over three amplification stages within the Rx path. Upon power-up, the RxPGA gain register is set to its minimum gain of -12 dB. The RxPGA gain mapping is shown in Figure 15.
48 42 36 30 24
GAIN (dB)
Updating the RxPGA via the Tx[5:0] port is an option only in full-duplex mode 1 . In this case, a high level on the GAIN pin 2 with TXSYNC low programs the PGA setting on either the rising edge or falling edge of RXCLK, as shown in Figure 16. The GAIN pin must be held high, TXSYNC must be held low, and gain data must be stable for one or more clock cycles to update the RxPGA gain setting. A low level on the GAIN pin enables data to be fed to the digital interpolation filter. This interface should be considered when upgrading existing designs from the AD9875/AD9876 MxFE products or from half-duplex applications trying to minimize an ASIC pin count.
tSU
RXCLK
18 12 6 0 -6 0 6 12 18 24 30 36 42 48 54 6-BIT DIGITAL WORD-DECIMAL EQUIVALENT 60 66
06733-015
TXSYNC Tx[5:0]
tHD
GAIN
06733-016
GAIN
Figure 16. Updating RxPGA via Tx[5:0] in Full-Duplex Mode
-12
Figure 15. Digital Gain Mapping of RxPGA
Table 15 lists the SPI registers pertaining to the RxPGA. Table 15. SPI Registers for RxPGA Control
Address (Hex) 0x09 0x0B Bit 6 5:0 6 5 3 2 1 Description Enable RxPGA update via SPI. RxPGA gain code. Select TxPGA via PGA[5:0]. Select RxPGA via PGA[5:0]. Enable software gain strobe, full-duplex. Enable RxPGA update via Tx[5:0], full-duplex. 3-Bit RxPGA gain mapping, half-duplex.
Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an option for both the half-duplex 3 and full-duplex interface. The PGA port consists of an input buffer that passes the 6-bit data appearing at its input directly to the RxPGA (or TxPGA) gain register with no gating signal required. Bit 5 or Bit 6 of Register 0x0B is used to select whether the data updates the RxPGA or TxPGA gain register. In applications that switch between RxPGA and TxPGA gain control via PGA[5:0], be sure that the RxPGA (or TxPGA) is not inadvertently loaded with the wrong data during a transition. In the case of an RxPGA-to-TxPGA transition, first deselect the RxPGA gain register, update the PGA[5:0] port with the desired TxPGA gain setting, and then select the TxPGA gain register. Note that a silicon bug exists with the full-duplex interface (MODE = 1), which requires that the GAIN/PGA[5] pin remains low for the digital Tx path to remain enabled. Fullduplex protocol applications must use the SPI port to control the Tx and Rx gain. Half-duplex protocol applications using the function can use an AND gate with TXQUIET and the PGA5 bit serving as inputs to ensure that the GAIN/PGA[5] pin remains low during a Tx operation.
The RxPGA gain register can be updated via the Tx[5:0] port, the PGA[5:0] port, or the SPI port. The first two methods allow fast updates of the RxPGA gain register and should be considered for digital AGC functions requiring a fast closed-loop response. The SPI port allows direct update and readback of the RxPGA gain register via Register 0x09 with an update rate limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6 of Register 0x09 must be set for a read or write operation.
1 2
Default setting for full-duplex mode (MODE = 1). The gain strobe can also be set in software via Register 0x0B, Bit 3 for continuous updating. This eliminates the requirement for the external gain signal, reducing the ASIC pin count by 1. 3 Default setting for half-duplex mode (MODE = 0).
Rev. 0 | Page 19 of 36
AD9868
TxPGA CONTROL
The AD9868 also contains a digital PGA in the Tx path distributed between the TxDAC and IAMP. The TxPGA is used to control the peak current from the TxDAC and IAMP over a 7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution. A 6-bit word is used to set the TxPGA attenuation according to the mapping shown in Figure 17. The TxDAC gain mapping is applicable only when Bit 0 of Register 0x0E is set, and only when the 4 LSBs of the 6-bit gain word are relevant.
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20
The TxPGA register can be updated via the PGA[5:0] port or SPI port. The first method should be considered for fast updates of the TxPGA register. Its operation is similar to the description in the RxPGA Control section. The SPI port allows direct update and readback of the TxPGA register via Register 0x0A with an update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of Register 0x0A must be set for a read or write operation. Table 16 lists the SPI registers pertaining to the TxPGA. The TxPGA control register default setting is for minimum attenuation (0 dBFS) with the PGA[5:0] port disabled for Tx gain control. Table 16. SPI Registers TxPGA Control
Address (Hex) 0x0A Bit 6 5:0 6 5 0 Description Enable TxPGA update via SPI. TxPGA gain code. Select TxPGA via PGA[5:0]. Select RxPGA via PGA[5:0]. TxDAC output (IAMP disabled).
Tx ATTENUATION (dBFS)
TxDACs IOUTP OUTPUT HAS 7.5dB RANGE
0x0B 0x0E
0
8
16
24
32
40
48
56
64
6-BIT DIGITAL CODE (Decimal Equivalent)
Figure 17. Digital Gain Mapping of TxPGA
06733-017
IAMPs IOUTN OUTPUT HAS 19.5dB RANGE
Rev. 0 | Page 20 of 36
AD9868 TRANSMIT PATH
The transmit path of the AD9868 (or its related part, the AD9869) of a selectable digital 2x/4x interpolation filter, a 10-bit (or12-bit) TxDAC, and a current-output amplifier, IAMP (see Figure 18). Note that the additional two bits of resolution offered by the AD9869 result in a 10 dB to 12 dB reduction in the pass-band noise floor. The digital interpolation filter relaxes the Tx analog filtering requirements by simultaneously reducing the images from the DAC reconstruction process while increasing the analog filter's transition band. The digital interpolation filter can also be bypassed, resulting in lower digital current consumption.
IOUTP+ IOUTP-
These responses also include the inherent sinc(x) from the TxDAC reconstruction process and can be used to estimate any post analog filtering requirements. The pipeline delays of the 2x and 4x filter responses are 21.5 clock cycles and 24 clock cycles, respectively, relative to fDATA. The filter delay is also taken into consideration for applications configured for a half-duplex interface with the halfduplex power-down mode enabled. This feature allows the user to set a programmable delay that powers down the TxDAC and IAMP only after the last Tx input sample has propagated through the digital filter. See the Power Control and Dissipation section for more details.
10 2.5 WIDE BAND 0 -10 2.0 1.5 1.0 0.5 PASS BAND -1.0dB @ 0.441 fDATA 0 -0.5 -1.0 -1.5 -2.0 0 0.25 0.50 0.75 1.00 1.25 1.75 1.50 NORMALIZED FREQUENCY (Relative to fDATA)
06733-019 06733-020
ADIO[9:4]/ Tx[5:0]
10
2-4x
TxDAC
IAMP 0 TO -12dB
IOUTN+ IOUTN-
ADIO[3:0]/ Rx[5:2]
WIDEBAND RESPONSE (dB)
-20 -30 -40 -50 -60 -70 -80 -90
AD9868
06733-018
TXEN/SYNC TXCLK
Figure 18. Functional Block Diagram of Tx Path
DIGITAL INTERPOLATION FILTERS
The input data from the Tx port can be fed into a selectable 2x/4x interpolation filter. The interpolation factor for the digital filter is set via SPI Register 0x0C with the settings shown in Table 17. The maximum input word rate, fDATA, into the interpolation filter is 80 MSPS; the maximum DAC update rate is 200 MSPS. Therefore, applications with input word rates at or below 50 MSPS can benefit from 4x interpolation, whereas applications with input word rates between 50 MSPS and 80 MSPS can benefit from 2x interpolation. Table 17. Interpolation Factor Set via SPI Register 0x0C
Bits 7:6] 00 01 10 11 Interpolation Factor 4 2 Do not use Do not use
-2.5 2.00
Figure 19. Frequency Response of 2x Interpolation Filter (Normalized to fDATA)
10 WIDE BAND 0 -10 2.0 1.5 1.0 0.5 PASS BAND 0 -1.0dB @ 0.45 fDATA -0.5 -1.0 -1.5 -2.0 0 0.5 1.0 1.5 2.0 2.5 3.5 3.0 NORMALIZED FREQUENCY (Relative to fDATA) -2.5 4.0 2.5
WIDEBAND RESPONSE (dB)
-20 -30 -40 -50 -60 -70 -80 -90
The interpolation filter consists of two cascaded half-band filter stages with each stage providing 2x interpolation. The first stage filter consists of 43 taps. The second stage filter, operating at the higher data rate, consists of 11 taps. The normalized wideband and pass-band filter responses (relative fDATA) for the 2x low-pass interpolation filter and 4x low-pass interpolation filter are shown in Figure 19 and Figure 20, respectively.
Figure 20. Frequency Response of 4x Interpolation Filter (Normalized to fDATA)
Rev. 0 | Page 21 of 36
PASS-BAND RESPONSE (dB)
PASS-BAND RESPONSE (dB)
0 TO -7.5dB
AD9868
TxDAC AND IAMP ARCHITECTURE
The Tx path contains a TxDAC with a current amplifier, IAMP. The TxDAC reconstructs the output of the interpolation filter and sources a differential current output that can be directed to an external load or fed into the IAMP for further amplification. The TxDAC and IAMP peak current outputs are digitally programmable over a 0 dB to -7.5 dB and 0 dB to -19.5 dB range, respectively, in 0.5 dB increments. Note that this assumes default register settings for Register 0x10 and Register 0x11. Applications demanding the highest spectral performance and/or lowest power consumption can use the TxDAC output directly. The TxDAC is capable of delivering a peak signal power-up to 10 dBm while maintaining respectable linearity performance. For power-sensitive applications requiring the highest Tx power efficiency, the TxDAC full-scale current output can be reduced to as low as 2 mA, and its load resistors sized to provide a suitable voltage swing that can be amplified by a low power, op amp-based driver. Most applications requiring higher peak signal powers (up to 17 dBm) should use the IAMP. The IAMP can be configured as a current source for loads having a well-defined impedance (50 or 75 systems). Figure 21 shows the equivalent schematic of the TxDAC and IAMP. The TxDAC provides a differential current output appearing at IOUTP+ and IOUTP-. The TxDAC can also be modeled as a differential current source generating a signaldependent ac current, when IS has a peak current of I along with two dc current sources, sourcing a standing current equal to I. The full-scale output current, IOUTP_FS, is equal to the sum of these standing current sources (IOUTP_FS = 2 x I).
N x (I + I) N x (I - I)
The value of I is determined by the RSET value at the REFADJ pin along with the Tx path's digital attenuation setting. With 0 dB attenuation, the value of I is I = 16 x (1.23/RSET) (1)
For example, an RSET value of 1.96 k results in I equal to 10.0 mA with IOUTP_FS equal to 20.0 mA. Note that the REFIO pin provides a nominal band gap reference voltage of 1.23 V and should be decoupled to analog ground via a 0.1 F capacitor. The differential current output of the TxDAC is always connected to the IOUTP pins, but it can be directed to the IAMP by clearing Bit 0 of Register 0x0E. As a result, the IOUTP pins must remain completely open if the IAMP is to be used. The IAMP consists of programmable current mirrors providing a gain factor of N that is programmable from 0 to 4 in steps of 1 (via Bits[2:0] of Register 0x10 with a default setting of N = 4). Bit 7 of this register must be set to overwrite the default settings of this register. The maximum peak current per output is 100 mA and occurs when the TxDAC standing current, I, is set for 12.5 mA (IOUTP_FS = 25 mA). Because the current mirrors consist of NMOS devices, they sink current. Therefore, each output pin requires a dc current path to a positive supply. The voltage output of each output pin is allowed to swing between 0.5 V and 3.9 V. Lastly, both the standing current, I, and the ac current, IS, from the TxDAC are amplified by the gain factor (N) with the total standing current drawn from the positive supply being equal to 2 x (N) x I (2)
IOUTN+
I REFADJ REFIO RSET 0.1F I + I I - I IOUTP+ IOUTP-
IS
I
IOFF1
IOFF1
IOUTN-
TxDAC
Programmable current sources, IOFF1 via Register 0x12, can be used to improve the linearity performance under certain conditions by increasing their signal-to-standing current ratios. This feature provides a marginal improvement in distortion performance under large signal conditions when the peak ac current of the reconstructed waveform frequently approaches the dc standing current within the TxDAC (0 dBFS to -1 dBFS sine wave) causing the internal mirrors to turn off. However, the improvement in distortion performance diminishes as the crest factor (peak-to-rms ratio) of the ac signal increases. Most applications can disable these current sources (set to 0 mA via Register 0x12) to reduce the IAMP current consumption. Table 18. SPI Registers for TxDAC and IAMP
Address (Hex) 0x0E 0x10 Bit 0 7 2:0 2:0 Description TxDAC output. Enable current mirror gain settings. Primary path NMOS gain of 0 to 4 with = 1. IOFF1 standing current.
xN
xN
06733-021
IAMP
Figure 21. Equivalent Schematic of TxDAC and IAMP
0x12
Rev. 0 | Page 22 of 36
AD9868
Tx PROGRAMMABLE GAIN CONTROL
TxPGA functionality is also available to set the peak output current from the TxDAC or IAMP. The TxDAC and IAMP are digitally programmable via the PGA[5:0] port or SPI over a 0 dB to -7.5 dB range and 0 dB to -19.5 dB range, respectively, in 0.5 dB increments. The TxPGA can be considered as two cascaded attenuators with the TxDAC providing a 7.5 dB range in 0.5 dB increments, and the IAMP providing a 12 dB range in 6 dB increments. As a result, the IAMP composite 19.5 dB span is valid only if Register 0x10 remains at its default setting of 0x04. Modifying this register setting corrupts the LUT and results in an invalid gain mapping. Optimum distortion performance can typically be achieved by performing both of the following: * Limiting the peak positive VIOUTP+ and VIOUTP- to 0.8 V to avoid onset of TxDAC output compression (TxDAC voltage compliance is around 1.2 V). Limiting V p-p seen at IOUTP+ and IOUTP- to less than 1.6 V.
*
Applications demanding higher output voltage swings and power drive capabilities can benefit from using the IAMP.
IAMP CURRENT-MODE OPERATION
The IAMP can be configured for the current-mode operation (see Figure 23) for loads remaining relatively constant. In this mode, the IAMP delivers the signal-dependent current to the load via a center-tap transformer. Because the mirrors exhibit a high output impedance, they can be easily back-terminated (if required).
AVDD 0.1F RSET 0.1F IOUTN+ IOUTPK IOUTN- IOUTPK = N x I POUTPK = (IOUTPK)2 x T2 x RL RCM
TxDAC OUTPUT OPERATION
The differential current output of the TxDAC is available at the IOUTP+ and IOUTP- pins, and the IAMP should be disabled by setting Bit 0 of Register 0x0E. Any load connected to these pins must be ground referenced to provide a dc path for the current sources. Figure 22 shows the outputs of the TxDAC driving a doubly terminated 1:1 transformer with its center tap tied to ground. The peak-to-peak voltage, V p-p, across RL (and IOUTP+ to IOUTP-) is equal to 2 x I x (RL||RS). With I = 10 mA and RL = RS = 50 , V p-p is equal to 0.5 V with 1 dBm of peak power being delivered to RL and 1 dBm being dissipated in RS.
1:1 RS RSET RL
IOUTP+
REFIO
REFADJ
IOUTP-
IBIAS = 2 x N x I
T:1 RL
TxDAC
IAMP
0.1F
0 TO -7.5dB
0 TO -12dB
REFADJ
IOUTP+
IOUTP-
REFIO
IOUTN+ IAMP
Figure 23. Current-Mode Operation
TxDAC
0 TO -7.5dB
0 TO -12dB
IOUTN-
06733-022
Figure 22. TxDAC Output Directly via Center-Tap Transformer
The TxDAC is capable of delivering up to 10 dBm peak power to a load, RL. To increase the peak power for a fixed standing current, users must increase V p-p across IOUTP+ and IOUTP- by increasing one or more of the following parameters: RS, RL (if possible), and/or the turns ratio, N, of the transformer. For example, removing the RS from Figure 22 and applying a 2:1 impedance ratio transformer results in 10 dBm of peak power capabilities to the load. Note that increasing the power output capabilities of the TxDAC reduces the distortion performance due to the higher voltage swings seen at IOUTP+ and IOUTP-.
The IAMP gain, N, can be set between 0 and 4, while the TxDAC standing current, I, can be set between 2 mA and 12.5 mA (with the IOUTP outputs left open). The IOUTN outputs should be connected to the transformer, which needs to be specified to handle the dc standing current, IBIAS, that is drawn by the IAMP. In addition, because IBIAS remains signal independent, a series resistor should be inserted between AVDD and the center-tap transformer to provide provisions such that the IAMP common-mode voltage, VCM, can be reduced since its optimum linearity performance is sensitive to both the Tx signal's peak-to-rms characteristics as well as the IAMP VCM. Note that the VCM bias should not exceed 3.3 V. The power dissipated in the IAMP alone is as follows: PIAMP = 2 x N x I x VCM (3)
Rev. 0 | Page 23 of 36
06733-023
AD9868 RECEIVE PATH
The receive signal path for the AD9868 (or its related part, the AD9869) consists of a 3-stage RxPGA, a 3-pole programmable LPF, and a 10-bit (or 12-bit) ADC (see Figure 24). Note that the additional two bits of resolution offered by the AD9869 result in a 3 dB to 5 dB lower noise floor, depending on the RxPGA gain setting and LPF cutoff frequency. Also working in conjunction with the receive path is an offset correction circuit. These blocks are discussed in detail in the following sections. Note that the power consumption of the RxPGA can be modified via Register 0x13 as discussed in the Power Control and Dissipation section.
ADIO[9:4]/ Tx[5:0]
The PGA input is self-biased at a 1.3 V common-mode level, allowing maximum input voltage swings of 1.5 V at RX+ and RX-. AC-coupling the input signal to this stage via 0.1 F coupling capacitors is recommended to ensure that any external dc offset does not become amplified with high RxPGA gain settings, potentially exceeding the ADC input range. To limit the RxPGA self-induced input offset, an offset cancellation loop is included. This cancellation loop is automatically performed upon power-up and can also be initiated via the SPI. During calibration, the RxPGA first stage is internally shorted, and each gain stage set to a high gain setting. A digital servo loop slaves a calibration DAC, which forces the Rx input offset to be within 32 LSBs for this particular high gain setting. Although the offset varies for other gain settings, the offset is typically limited to 5% of the ADC 2 V input span. Note that the offset cancellation circuitry is intended to reduce the voltage offset attributed to only the RxPGA input stage, not to any dc offsets attributed to an external source. The gain of the RxPGA should be set to minimize clipping of the ADC while utilizing most of its dynamic range. The maximum peak-to-peak differential voltage that does not result in ADC clipping is shown in Figure 25. Although the graph suggests that the maximum input signal for a gain setting of -12 dB is 8.0 V p-p, the maximum input voltage into the PGA should be limited to less than 6 V p-p to prevent turning on ESD protection diodes. For applications having higher maximum input signals, consider adding an external resistive attenuator network. While the input sensitivity of the Rx path is degraded by the amount of attenuation on a dB-to-dB basis, the low noise characteristics of the RxPGA provide some design margin such that the external line noise remains the dominant source.
FULL-SCALE PEAK-TO-PEAK INPUT SPAN (V)
CLK SYNC. 2M CLK MULTIPLIER
CLKOUT1 CLKOUT2 OSCIN XTAL RX+
1-POLE LPF
ADIO[3:0]/ Rx[5:2] RXEN/SYNC RXCLK 10/12 ADC 80MSPS
SPGA
0 TO 6dB = 1dB
2-POLE LPF
RX-
-6 TO 18dB = 6dB
-6 TO 24dB = 6dB
PGA[5:0] PORT SPI PORT
6 4 REGISTER CONTROL
GAIN MAPPING LUT
AD9868
Figure 24. Functional Block Diagram of Rx Path
Rx PROGRAMMABLE GAIN AMPLIFIER
The RxPGA has a digitally programmable gain range from -12 dB to +48 dB with 1 dB resolution via a 6-bit word. Its purpose is to extend the dynamic range of the Rx path such that the input of the ADC is presented with a signal that scales within its fixed 2 V input span. There are multiple ways of setting the RxPGA gain as discussed in the RXPGA Control section, as well as an alternative 3-bit gain mapping having a range of -12 dB to +36 dB with a +8 dB resolution. The RxPGA is comprised of two sections: a continuous time PGA (CPGA) for course gain and a switched capacitor PGA (SPGA) for fine gain resolution. The CPGA consists of two cascaded gain stages providing a gain range of -12 dB to +42 dB with a 6 dB resolution. The first stage features a low noise preamplifier (<3.0 nV/Hz), thereby eliminating the need for an external preamplifier. The SPGA provides a gain range of 0 dB to 6 dB with a 1 dB resolution. A look-up table (LUT) is used to select the appropriate gain setting for each stage. The nominal differential input impedance of the RxPGA input appearing at the device RX+ and RX- input pins is 400 ||4 pF (20%) and remains relatively independent of gain setting.
06733-024
8.0000 4.0000 2.0000 1.0000 0.5000 0.2500 0.1250 0.0625 0.0312 0.0156 0.0100 -12
06733-025
-6
0
6
12
18 GAIN (dB)
24
30
36
42
48
Figure 25. Maximum Peak-to-Peak Input vs. RxPGA Gain Setting that Does Not Result in ADC Clipping
Rev. 0 | Page 24 of 36
AD9868
LOW-PASS FILTER
The low-pass filter (LPF) provides a third-order response with a cutoff frequency that is typically programmable over a 15 MHz to 35 MHz span. The first real pole is implemented within the first CPGA gain stage (see Figure 24), and the complex pole pair is implemented in the second CPGA gain stage. Capacitor arrays are used to vary the different RC time constants within these two stages in a manner that changes the cutoff frequency while preserving the normalized frequency response. Because absolute resistor and capacitor values are process-dependent, a calibration routine lasting less than 100 s automatically occurs each time the target cutoff frequency register (Register 0x08) is updated, ensuring a repeatable cutoff frequency from device to device. Although the default setting specifies that the LPF be active, it can also be bypassed providing a nominal f-3 dB of 55 MHz. Table 19 shows the SPI registers pertaining to the LPF. Table 19. SPI Registers for Rx Low-Pass Filter
Address (Hex) 0x07 0x08 Bit 0 7:0 Description Enable Rx LPF. Target value.
0.25 0 -0.25 -0.50 -0.75 -1.00
GAIN (dB)
1.30 NORMALIZED GAIN RESPONSE 1.25 1.20
NORMALIZED GROUP DELAY TIME RESPONSE (GDT)
06733-028
1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 NORMALIZED GROUP DELAY 0.75 0.70 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-1.25 -1.50 -1.75 -2.00 -2.25 -2.50 -2.75 -3.00
NORMALIZED FREQUENCY
Figure 27. LPF Normalized Pass-Band Gain and Group Delay Responses
The f-3 dB is programmable by writing an 8-bit word, referred to as the target, to Register 0x08. The cutoff frequency is a function of the ADC sample rate, fADC, and to a lesser extent, the RxPGA gain setting (in dB). Figure 28 shows how f-3 dB varies as a function of the RxPGA gain setting.
3 0 -3 -6 -9 -12 -15 -18 -6dB GAIN 0dB GAIN +6dB GAIN +18dB GAIN +30dB GAIN +42dB GAIN
Actual GDT = Normalized GDT/(2.45 x f-3dB)
5 0 -5 -10
GAIN (dB)
(4)
FUNDAMENTAL (dB)
The normalized wideband gain response is shown in Figure 26. The normalized pass-band gain and group delay responses are shown in Figure 27. The -3 dB cutoff frequency, f-3 dB, results in -3 dB attenuation. In addition, the actual group delay time (GDT) response can be calculated given a programmed cutoff frequency using the following equation:
0
5
10
15
20
25
30
35
40
45
50
INPUT FREQUENCY (MHz)
Figure 28. Effects of RxPGA Gain on LPF Frequency Response (f-3 dB = 32 MHz @ 0 dB and fADC = 80 MSPS)
-15 -20 -25 -30
06733-026
The following formula 1 can be used to estimate f-3 dB for a RxPGA gain setting of 0 dB: f-3dB_0dB = (128/target) x (fADC/80) x(fADC/30 + 23.83) f (5)
-35
0
0.5
1.0
1.5 FREQUENCY
2.0
2.5
3.0
Figure 29 compares the measured and calculated f-3 dB using this formula.
Figure 26. LPF Normalized Wideband Gain Response
1
Empirically derived for an f-3 dB range of 15 MHz to 35 MHz and an fADC of 40 MSPS to 80 MSPS with an RxPGA = 0 dB.
Rev. 0 | Page 25 of 36
06733-027
0.65 1.0
AD9868
35 33 31
FREQUENCY (MHz)
ANALOG-TO-DIGITAL CONVERTER (ADC)
The AD9868 features a 10-bit analog-to-digital converter (ADC) capable of up to 80 MSPS. As shown in Figure 24, the ADC is driven by the SPGA stage, which performs both the sample-and-hold and the fine gain adjust functions. A buffer amplifier (not shown) isolates the last CPGA gain stage from the dynamic load presented by the SPGA stage. The full-scale input span of the ADC is 2 V p-p, and depending on the PGA gain setting, the full-scale input span into the SPGA is adjustable from 1 V to 2 V in 1 dB increments.
224
29 27 25 23 21 19 17 50MSPS MEASURED 50MSPS CALCULATED 64 80 96 112 128 144 160 176 192 208 TARGET-DECIMAL EQUIVALENT
06733-029
80MSPS MEASURED 80MSPS CALCULATED
15 48
Figure 29. Measured and Calculated f-3 dB vs. Target Value for fADC = 50 MSPS and 80 MSPS
The following scaling factor can be applied to the previous formula to compensate for the RxPGA gain setting on f-3 dB: Scale Factor = 1 - (RxPGA in dB)/382 (6)
A pipelined, multistage ADC architecture is used to achieve high sample rates while consuming low power. The ADC distributes the conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage on each clock edge. The ADC typically performs best when driven internally by a 50% duty cycle clock. The ADC power consumption can be reduced by 25 mA with minimal effect on its performance by setting Bit 4 of Register 0x07. Alternative power bias settings are also available via Register 0x13, as discussed in the Power Control and Dissipation section. Lastly, the ADC can be completely powered down for half-duplex operation, further reducing the peak power consumption of the AD9868. The ADC has an internal voltage reference and reference amplifier as shown in Figure 31. The internal band gap reference generates a stable 1 V reference level that is converted to a differential 1 V reference centered about midsupply (AVDD/2). The outputs of the differential reference amplifier are available at the REFT and REFB pins and must be properly decoupled for optimum performance. The REFT and REFB pins are conveniently situated at the corners of the LFCSP package such that C1 (0603 type) can be placed directly across its pins. C3 and C4 can be placed underneath C1, and C2 (10 F tantalum) can be placed furthest from the package.
REFT TO ADCs C3 0.1F C2 10F
This scaling factor reduces the calculated f-3 dB as the RxPGA increases. Applications that need to maintain a minimum cutoff frequency, f-3 dB_MIN, for all RxPGA gain settings should first determine the scaling factor for the highest RxPGA gain setting to be used. Next, the f-3 dB_MIN should be divided by this scale factor to normalize to the 0 dB RxPGA gain setting, f-3 dB_0 dB. Equation 5 can then be used to calculate the target value. The LPF frequency response shows a slight sensitivity to temperature, as shown in Figure 30. Applications sensitive to temperature drift can recalibrate the LPF by rewriting the target value to Register 0x08.
35
30
FREQUENCY (MHz)
fOUT ACTUAL 80MHz AND -40C
25
fOUT ACTUAL 80MHz AND +25C fOUT ACTUAL 80MHz AND +85C
C1 0.1F REFB 1.0V
20
C4 0.1F
112
128
144
160
176
192
208
224
240
TARGET-DECIMAL EQUIVALENT
Figure 30. f-3 dB Temperature Drift for fADC = 80 MSPS and RxPGA = 0 dB
TOP VIEW
06733-030
15 96
C3 C1 C4 C2
06733-031
Figure 31. ADC Reference and Decoupling
Rev. 0 | Page 26 of 36
AD9868
Table 20 shows the SPI registers pertaining to the ADC. Table 20. SPI Registers for Rx ADC
Address (Hex) 0x04 0x07 0x13 Bit 4 4 2:0 Description ADC clock from PLL. ADC low power mode. ADC power bias adjust.
AGC TIMING CONSIDERATIONS
When implementing a digital AGC timing loop, it is important to consider the Rx path latency and settling time of the Rx path in response to a change in gain setting. While the RxPGA settling time may also show a slight dependency on the LPF cutoff frequency, the ADC pipeline delay, along with the ADIO bus interface, presents a more significant delay. The amount of delay or latency is dependent on whether a half-duplex or fullduplex is selected. An impulse response at the RxPGA input can be observed after 10.0 ADC clock cycles (1/fADC) in the case of a half-duplex interface, and 10.5 ADC clock cycles in the case of a full-duplex interface. This latency, along with the RxPGA settling time, should be considered to ensure stability of the AGC loop.
Rev. 0 | Page 27 of 36
AD9868 CLOCK SYNTHESIZER
The AD9868 generates all its internal sampling clocks, as well as two user-programmable clock outputs appearing at CLKOUT1 and CLKOUT2, from a single reference source (see Figure 32). The reference source can either be a fundamental frequency or an overtone quartz crystal connected between OSCIN and XTAL, with the parallel resonant load components specified by the crystal manufacturer. It can also be a TTL-level clock applied to OSCIN with XTAL left unconnected. frequency between 100 MHz and 200 MHz. The VCO output drives the TxDAC directly such that its update rate, fDAC, is related to fOSCIN by the following equation: fDAC = 2M x fOSCIN where M = 0, 1, 2, or 3. M is the PLL multiplication factor set in Register 0x04. The value of M is determined by the Tx path's word rate, fDATA, and digital interpolation factor, F, as shown in the following equation: M = log2(F x fDATA/fOSCIN)
TO TxDAC
(7)
XTAL
XTAL C1
C2
/2N CLK MULTIPLIER 2M
TO ADC
OSCIN
(8)
CLKOUT2 CLKOUT1
/2L /2R
/F/2
RXCLK (FULL-DUPLEX ONLY)
Figure 32. Clock Oscillator and Synthesizer
Note that if the reference frequency appearing at OSCIN is chosen to be equal to the Tx path and Rx path word rates, M is equal to log2(F). Also note that the RXCLK frequency for full-duplex mode (MODE = 1) is a function of the 2M CLK multiplier setting, as well as the interpolation factor, F. Full-duplex mode requires that RXCLK be equal to 2 x fDATA because data is transferred in nibbles. The clock source for the ADC can be selected in Register 0x04 as a buffered version of the reference frequency appearing at OSCIN (default setting) or a divided version of the VCO output, fDAC. The first option is the default setting and most desirable if fOSCIN is equal to fADC. This option typically results in the best jitter/phase noise performance for the ADC sampling clock. The second option is suitable in cases where fOSCIN is a factor of 2 or 4 less than the fADC. In this case, the divider ratio, N, is chosen such that the divided down VCO output is equal to the ADC sample rate, as shown in the following equation: fADC = fDAC/2N where N = 0, 1, or 2. (9)
Special consideration should be given to the design of crystal oscillators using the AD9868 internal CMOS inverter. This is especially true when designing third overtone oscillators where crystal power dissipation and negative resistance upon start-up are a few of the issues to consider. For this reason, a 40 MHz or lower fundamental crystal is preferred with the AD9868. The CMOS inverter device characteristics are listed in Table 21. It is recommended to consult with the selected crystal manufacturer to ensure that a robust design can be realized with the selected crystal and AD9868 CMOS inverter. Table 21. CMOS Inverter Device Characteristics
Parameter RF gm ZOUT CIN COUT Nominal Value 1.2 M 17 mA/V 1.6 k 2.5 pF 2.0 pF Tolerance % 25 20 50 25 25 Description Feedback resistor. At midsupply. At midsupply. Parasitic capacitance. Parasitic capacitance.
06733-032
The data rate, fDATA, for the Tx and Rx data paths must always be equal. Therefore, the ADC sample rate, fADC, is always equal to fDATA, while the TxDAC update rate is a factor of 1, 2, or 4 of fDATA, depending on the selected interpolation factor. The data rate refers to the word rate and should not be confused with the nibble rate in full-duplex interface. The 2M CLK multiplier contains a PLL (with integrated loop filter) and a VCO capable of generating an output frequency that is a multiple of 1, 2, 4, or 8 of its input reference frequency, fOSCIN, appearing at OSCIN. The input frequency range of fOSCIN is between 20 MHz and 80 MHz, and the VCO can operate over an 80 MHz to 200 MHz span. For the best phase noise/jitter characteristics, it is advisable to operate the VCO with a
The CLK synthesizer also has two clock outputs appearing at CLKOUT1 and CLKOUT2. They are programmable via Register 0x06. Both outputs can be inverted or disabled. The voltage levels appearing at these outputs are relative to DRVDD and remain active during a hardware or software reset. Table 22 shows the SPI registers pertaining to the CLK synthesizer. Table 22. SPI Registers for CLK Synthesizer
Address (Hex) 0x04 Bit 4 3:2 1:0 7:6 5 4 3:2 1 0 Description ADC CLK from PLL. PLL divide factor (N). PLL multiplication factor (M). CLKOUT2 divide number. CLKOUT2 invert. CLKOUT2 disable. CLKOUT1 divide number. CLKOUT1 invert. CLKOUT1 disable.
0x06
Rev. 0 | Page 28 of 36
AD9868
CLKOUT1 is a divided version of the VCO output and can be set to be a submultiple integer of fDAC (fDAC/2R, where R = 0, 1, 2, or 3). Because this clock is derived from the same set of dividers used within the PLL core, it is phase-locked to the dividers such that its phase relationship relative to the signal appearing at OSCIN (or RXCLK) can be determined upon power-up. In addition, this clock has a near 50% duty cycle because it is derived from the VCO. As a result, CLKOUT1 should be selected before CLKOUT2 as the primary source for system clock distribution. CLKOUT2 is a divided version of the reference frequency, fOSCIN, and can be set to be a submultiple integer of fOSCIN (fOSCIN/2L, where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is a delayed version of the signal appearing at OSCIN, exhibiting the same duty cycle characteristics. With L set to 1 or 2, the output of CLKOUT2 is a divided version of the OSCIN signal, exhibiting a near 50% duty cycle, but without having a deterministic phase relationship relative to CLKOUT1 (or RXCLK).
Rev. 0 | Page 29 of 36
AD9868 POWER CONTROL AND DISSIPATION
POWER-DOWN
The AD9868 provides the ability to control the power-on state of various functional blocks. The state of the PWRDWN pin, along with the contents of Register 0x01 and Register 0x02, allow two user-defined power settings that are pin-selectable. The default settings1 are such that Register 0x01 has all blocks powered on (all bits 0), while Register 0x02 has all blocks powered down (excluding the PLL) such that the clock signal remains available at CLKOUT1 and CLKOUT2. When the PWRDWN pin is low, the functional blocks corresponding to the bits in Register 0x01 are powered down. When the PWRDWN is high, the functional blocks corresponding to the bits in Register 0x02 are powered down. PWRDWN immediately affects the designated functional blocks with minimum digital delay. Table 23. SPI Registers Associated with Power-Down and Half-Duplex Power Savings
Address (Hex) 0x01 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7:3 2 1 0 Description CLK Synthesizer TxDAC/IAMP Tx Digital REF ADC CML ADC PGA Bias RxPGA CLK Synthesizer TxDAC/IAMP Tx Digital REF ADC CML ADC PGA Bias RxPGA Tx OFF Delay Rx PWRDWN via TXEN Enable Tx PWRDWN Enable Rx PWRDWN Comments PWRDWN = 0. Default setting is all functional blocks powered on.
HALF-DUPLEX POWER SAVINGS
Significant power savings can be realized in applications having a half-duplex protocol, allowing only the Rx path or Tx path to be operational at one time. The power-savings method depends on whether the AD9868 is configured for a full-duplex or halfduplex interface. Functional blocks having fast power-on/power-off times for the Tx path and Rx path are controlled by the following bits: TxDAC/IAMP, Tx Digital, ADC, and RxPGA (see Table 23). In the case of a full-duplex digital interface (MODE = 1), users can set Register 0x01 to Register 0x60 and Register 0x02 to Register 0x05 (or vice versa) such that the Tx path and Rx path are never powered on simultaneously. The PWRDWN pin can then be used to control which path is powered on, depending on the burst type. During a Tx burst, the Rx path PGA and ADC blocks can typically be powered down within 100 ns, while the Tx path DAC, IAMP, and digital filter blocks are powered up within 0.5 s. For an Rx burst, the Tx circuitry can be powered down within 100 ns, while the Rx circuitry is powered up within 2 s. Setting the TXQUIET pin low allows it to be used with the fullduplex interface to quickly power down the IAMP and disable the interpolation filter. This is meant to maintain backward compatibility with the AD9875/AD9876 MxFEs, except that the TxDAC remains powered if its IOUTP outputs are used. In most applications, the interpolation filter needs to be flushed with 0s before or after being powered down. This ensures that upon power-up, the TxDAC (and IAMP) have a negligible differential dc offset, thus preventing spectral splatter due to an impulse transient. Applications using a half-duplex interface (MODE = 0) can benefit from an additional power-savings feature available in Register 0x03. This register is effective only for a half-duplex interface. In addition to providing power savings for half-duplex applications, this feature allows the AD9868 to be used in applications that need only its Rx (or Tx) path functionality through pin strapping, making a serial port interface (SPI) optional. This feature also allows the PWRDWN pin to retain its default function as a master power control, as defined in Table 10. The default settings for Register 0x03 provide fast power control of the functional blocks in the Tx signal path and Rx signal path (outlined previously) using the TXEN pin. The TxDAC remains powered on in this mode, while the IAMP is powered down. Significant current savings are typically realized when the IAMP is powered down.
0x02
PWRDWN = 1. Default setting is all functional blocks powered off excluding PLL.
0x03
Half-duplex power savings.
1
With MODE = 1 and CONFIG =1, Register 0x02 default settings are with all blocks powered off, with RXCLK providing a buffered version of the signal appearing at OSCIN. This setting results in the lowest power consumption upon powerup, while still allowing AD9868 to generate the system clock via a crystal.
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AD9868
For a Tx burst, the falling edge of TXEN is used to generate an internal delayed signal for powering down the Tx circuitry. Upon receipt of this signal, power-down of the Tx circuitry occurs within 100 ns. The user-programmable delay for the Tx path power-down is meant to match the pipeline delay of the last Tx burst sample such that power-down of the TxDAC and IAMP does not impact its transmission. A 5-bit field in Register 0x03 sets the delay from 0 to 31 TXCLK clock cycles, with the default being 31 (0.62 s with fTXCLK = 50 MSPS). The digital interpolation filter is automatically flushed with midscale samples prior to power-down if the clock signal into the TXCLK pin is present for 33 additional clock cycles after TXEN returns low. For an Rx burst, the rising edge of TXEN is used to generate an internal signal (with no delay) that powers up the Tx circuitry within 0.5 s. The Rx path power-on/power-off can be controlled by either TXEN or RXEN by setting Bit 2 of Register 0x03. In the default setting, the falling edge of TXEN powers up the Rx circuitry within 2 s, while the rising edge of TXEN powers down the Rx circuitry within 0.5 s. If RXEN is selected as the control signal, its rising edge powers up the Rx circuitry, and the falling edge powers it down. To disable the fast power-down of the Tx circuitry and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0.
55 50 45
IAVDDTxDAC (mA)
40 35 30 25 20
06733-033
15 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13
ISTANDING (mA)
Figure 33. Reduction in TxDAC Supply Current vs. Standing Current
65 60 4x INTERPOLATION 55 50
IDVDD (mA)
45 40 2x INTERPOLATION 35 30 25 20 15 20 30 40 50 60 70 80 1x (HALF-DUPLEX ONLY)
06733-034
POWER REDUCTION OPTIONS
The power consumption of the AD9868 can be significantly reduced from its default setting by optimizing the power consumption vs. performance of the various functional blocks in the Tx signal path and Rx signal path. On the Tx path, minimum power consumption is realized when the TxDAC output is used directly and its standing current is reduced to as low as 1 mA. Although a slight degradation in THD performance results at reduced standing currents, it often remains adequate for most applications because the op amp driver typically limits the overall linearity performance of the Tx path. The load resistors used at the TxDAC outputs (IOUTP+ and IOUTP-) can be increased to generate an adequate differential voltage that can be further amplified via a power efficient op ampbased driver solution. Figure 33 shows how the supply current for the TxDAC is reduced from 55 mA to 14 mA as the standing current is reduced from 12.5 mA to 1.25 mA. Further Tx power savings can be achieved by bypassing or reducing the interpolation factor of the digital filter as shown in Figure 34.
INPUT DATA RATE (MSPS)
Figure 34. Digital Supply Current Consumption vs. Input Data Rate (DVDD = DRVDD = 3.3 V and fOUT = fDATA/10)
Power consumption on the Rx path can be achieved by reducing the bias levels of the various amplifiers contained within the RxPGA and ADC. As previously noted, the RxPGA consists of two CPGA amplifiers and one SPGA amplifier. The bias levels of each of these amplifiers, along with the ADC, can be controlled via Register 0x13 as shown in Table 24. The default setting for Register 0x13 is 0x00. Table 24. SPI Register for RxPGA and ADC Biasing
Address (Hex) 0x07 0x13 Bit 4 7:5 4:3 2:0 Description ADC low power. CPGA bias adjust. SPGA bias adjust. ADC power bias adjust.
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AD9868
Because the CPGA processes signals in the continuous time domain, its performance vs. bias setting remains mostly independent of the sample rate. Table 25 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits [7:5], while the remaining bits are maintained at their default settings of 0. Only four of the possible settings result in any reduction in current consumption relative to the default setting. Reducing the bias level typically results in degradation in the THD vs. frequency performance as shown in Figure 35. This is due to a reduction of the amplifier's unity gain bandwidth, while the SNR performance remains relatively unaffected. Table 25. Analog Supply Current vs. CPGA Bias Settings at fADC = 65 MSPS
Bit 7 0 0 0 0 1 1 1 1
65.0 SNR_RxPGA = 0dB 62.5 60.0 57.5 -25 -30 -35 SNR_RxPGA = 36dB
The SPGA is implemented as a switched capacitor amplifier, therefore, its performance vs. bias level is mostly dependent on the sample rate. Figure 36 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits [4:3] and sample rate, while the remaining bits are maintained at the default setting of 0. Figure 37 shows how the SNR and THD performance is affected for a 10 MHz sine wave input as the ADC sample rate is swept from 20 MHz to 80 MHz. The SNR and THD performance remains relatively stable, suggesting that the SPGA bias can often be reduced from its default setting without impacting the device's overall performance.
210 205 200 195 190 185 10 180
06733-036
Bit 6 0 0 1 1 0 0 1 1
Bit 5 0 1 0 1 0 1 0 1
mA 0 -27 -42 -51 -55 +27 +69 +27
-20
01
IAVDD (mA)
00
175 170 20
11
30
40
50
60
70
80
ADC SAMPLE RATE (MSPS)
Figure 36. AVDD Current vs. SPGA Bias Setting and Sample Rate
61 60 59 -54 -56 -58 SNR-00 SNR-01 SNR-10 SNR-11 -60
SNR (dBFS)
THD (dBc)
55.0 52.5 50.0 47.5 45.0 42.5 40.0 000
-40 -45 -50
58
SNR (dBc)
THD_RxPGA = 0dB
-55 -60 -65
06733-035
56 55 54 53 52 51 20 30 40 THD-00 THD-01 THD-10 THD-11
-64 -66 -68 -70 -72 60 70 -74 80
THD_RxPGA = 36dB 001 010 011 CPGA BIAS SETTING-BITS (7:5)
Figure 35. THD vs. fIN Performance and CPGA Bias Settings (000, 001, 010, 100 with RxPGA = 0 and +36 dB, AIN = -1 dBFS, LPF set to 26 MHz, fADC = 50 MSPS)
50
SAMPLE RATE (MSPS)
Figure 37. SNR and THD Performance vs. fADC and SPGA Bias Setting with RxPGA = 0 dB, fIN = 10 MHz, LPF set to 26 MHz, AIN = -1 dBFS
Rev. 0 | Page 32 of 36
06733-037
-70 100
THD (dBc)
57
-62
AD9868
The ADC is based on a pipeline architecture with each stage consisting of a switched capacitor amplifier. Therefore, its performance vs. bias level is mostly dependent on the sample rate. Figure 38 shows how the typical current consumption seen at AVDD varies as a function of Register 0x13, Bits [2:0] and sample rate, while the remaining bits are maintained at the default setting of 0. Setting Bit 4 or Register 0x07 corresponds to the 011 setting, and the settings of 101 and 111 result in higher current consumption. Figure 39 shows how the SNR and THD performance are affected for a 10 MHz sine wave input for the lower power settings as the ADC sample rate is swept from 20 MHz to 80 MHz.
220 210 200 190 001 101 OR 111
POWER DISSIPATION
The power dissipation of the AD9868 can become quite high in full-duplex applications in which the Tx path and Rx path are simultaneously operating with nominal power bias settings. In fact, some applications that use the IAMP may need to either reduce its peak power capabilities or reduce the power consumption of the Rx path so that the device's maximum allowable power consumption, PMAX, is not exceeded. PMAX is specified at 1.66 W to ensure that the die temperature does not exceed 125C at an ambient temperature of 85C. This specification is based on the 64-lead LFSCP having a thermal resistance, JA, of 24C/W with its heat slug soldered. (The JA is 30.8C/W if the heat slug remains unsoldered.) If a particular application's maximum ambient temperature, TA, falls below 85C, the maximum allowable power dissipation can be determined by the following equation: PMAX = 1.66 + (85 - TA)/24 (10)
000
IAVDD (mA)
180 170 160 150 140 100
010
011
101
Assuming the IAMP common-mode bias voltage is operating off the same analog supply as the AD9868, the following equation can be used to calculate the maximum total current consumption, IMAX, of the IC:
06733-038
130 120 20 30 40 50 60 70 80
IMAX = (PMAX - PIAMP)/3.47 With an ambient temperature of up to 85C, IMAX is 478 mA.
(11)
SAMPLE RATE (MSPS)
Figure 38. AVDD Current vs. ADC Bias Setting and Sample Rate
61 60 59 58 SNR-00 SNR-01 SNR-10 SNR-11 -54 -56 -58 -60
If the IAMP is operating off a different supply or in the voltage mode configuration, first calculate the power dissipated in the IAMP, PIAMP, using Equation 3, and then recalculate IMAX using Equation 11. Figure 33, Figure 34, Figure 36, and Figure 38 can be used to calculate the current consumption of the Rx and Tx paths for a given setting.
SNR (dBc)
56 55 54 53 52 51 20 30 40 THD-00 THD-01 THD-10 THD-11
-64 -66 -68 -70 -72 60 70 -74 80
THD (dBc)
57
-62
MODE SELECT UPON POWER-UP AND RESET
The AD9868 power-up state is determined by the logic levels appearing at the MODE and CONFIG pins. The MODE pin is used to select a half- or full-duplex interface by pin strapping it low or high, respectively. The CONFIG pin is used in conjunction with the MODE pin to determine the default settings for the SPI registers as outlined in Table 10. The intent of these particular default settings is to allow some applications to avoid using the SPI (disabled by pin strapping SEN high), thereby reducing implementation costs. For example, setting MODE low and CONFIG high configures the AD9868 to be backward compatible with the AD9975, while setting MODE high and CONFIG low makes it backward compatible with the AD9875. Other applications must use the SPI to configure the device.
50
SAMPLE RATE (MSPS)
Figure 39. SNR and THD Performance vs. fADC and ADC Bias Setting with RxPGA = 0 dB, fIN = 10 MHz, AIN = -1 dBFS
A sine wave input is a standard and convenient method of analyzing the performance of a system. However, the amount of power reduction that is possible is application dependent, based on the nature of the input waveform (such as frequency content, and peak-to-rms ratio), the minimum ADC sample, and the minimum acceptable level of performance. Thus, it is advisable that power-sensitive applications optimize the power bias setting of the Rx path using an input waveform that is representative of the application.
Rev. 0 | Page 33 of 36
06733-039
AD9868
A hardware reset (RESET pin) or software reset (Bit 5 of Register 0x00) can be used to place the AD9868 into a known state of operation as determined by the state of the MODE and CONFIG pins. A dc offset calibration and filter tuning routine is also initiated upon a hardware reset, but not with a software reset. Neither reset method flushes the digital interpolation filters in the Tx path. Refer to the Half-Duplex Mode and Full-Duplex Mode sections for information on flushing the digital filters. A hardware reset can be triggered by pulsing the RESET pin low for a minimum of 50 ns. The SPI registers are instantly reset to their default settings upon RESET going low, whereas the dc offset calibration and filter-tuning routine is initiated upon RESET returning high. To ensure sufficient power-on time of the various functional blocks, RESET returning high should occur no less than 10 ms upon power-up. If a digital reset signal from a microprocessor reset circuit (such as ADM1818) is not available, a simple R-C network referenced to DVDD can be used to hold RESET low for approximately 10 ms upon power-up. As a result, the analog loopback feature can be used for a halfduplex or full-duplex interface to allow testing of the functionality of the entire IC (excluding the digital data interface). For example, the user can configure the AD9868 with similar settings as the target system, inject an input signal (sinusoidal waveform) into the Rx input, and monitor the quality of the reconstructed output from the TxDAC or IAMP to ensure a minimum level of performance. In this test, the user can exercise the RxPGA as well as validate the attenuation characteristics of the RxLPF. Note that the RxPGA gain setting should be selected such that the input does not result in clipping of the ADC. Digital loopback can be used to test the full-duplex digital interface of the AD9868. In this test, data appearing on the Tx[5:0] port is routed back to the Rx[5:0] port, thereby confirming proper bus operation. The Rx port can also be three-stated for half-duplex and full-duplex interfaces. Table 26. SPI Registers for Test Modes
Address (Hex) 0x0D Bit 7 6 5 Description Analog loopback. Digital loopback. Rx port three-state.
ANALOG AND DIGITAL LOOPBACK TEST MODES
The AD9868 features analog and digital loopback capabilities that can assist in system debug and final test. Analog loopback routes the digital output of the ADC back into the Tx data path prior to the interpolation filters such that the Rx input signal can be monitored at the output of the TxDAC or IAMP.
Rev. 0 | Page 34 of 36
AD9868 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
48 49 PIN 1 INDICATOR
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
7.25 7.10 SQ 6.95
0.50 0.40 0.30
33
32
17 16
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF
0.25 MIN
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 40. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9868BCPZ 1 AD9868BCPZRL1
1
Temperature Range -40C to +85C -40C to +85C
Package Description 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ
Package Option CP-64-3 CP-64-3
Z = RoHS Compliant Part.
Rev. 0 | Page 35 of 36
063006-B
AD9868 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06733-0-5/07(0)
Rev. 0 | Page 36 of 36

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